Best Place To BuildSharan Srinivas | CTO, Mindgrove Technologies | “You have to be crazy to want to make silicon”| Ep.9
CHAPTERS
Mindgrove’s Series A: $8M raise + India’s DLI approval
Sharan opens by sharing Mindgrove’s Series A update, highlighting returning investors doubling down and two new funds joining the cap table. He also explains the Design Linked Incentive (DLI) scheme approval and how it de-risks early chip productization by tying incentives to milestones.
- •Series A totals ~$8M; previous investors doubled down plus Rocketship VC and Mela Ventures joined
- •DLI scheme approval: ~₹15 crores (~$2M) in incentives based on milestone achievement
- •Shift in pitch: from “we want to make a chip” to “we want to keep making and selling chips”
- •Why semiconductor investing is long-horizon and capital-intensive, especially in India
Semiconductors 101: why chips underpin almost everything digital
The conversation frames semiconductors as the foundation of modern digital life—from phones and cloud servers to UPI soundboxes and induction stoves. Sharan emphasizes that “digital” at any scale is impossible without chips and supporting electronic components.
- •Semiconductors enable cloud, storage, phones, payments, appliances, and power electronics
- •Everyday examples: UPI soundbox, smartphone camera/compute, digital switches and touch controls
- •Semiconductors include active chips plus passives (resistors/capacitors) in the broader ecosystem
- •The industry is vast because electronics have penetrated nearly every domain
The ecosystem map: fabless design, foundries, and integrated players
Sharan lays out the core business models: fabless design houses, pure-play foundries, and integrated device manufacturers. Mindgrove positions itself as a fabless company focused on design and sales while outsourcing fabrication and testing.
- •Mindgrove is fabless: design + sell; outsource manufacturing and test
- •Fabless examples: Qualcomm, Nvidia; integrated examples: Intel (and partially Samsung)
- •Pure-play foundry example: TSMC manufactures designs from others
- •Why business model choice matters: capex, speed, and specialization
From wafer to package: how chips are physically made and finished
The discussion walks through how a circular silicon wafer is patterned into many dies and then cut, packaged, and connected to the outside world. Sharan clarifies key terms like die, package, OSAT, and ATMP, connecting abstract jargon to the black chip packages people recognize.
- •12-inch wafer patterned; repeated “squares” (dies) are cut out after fabrication
- •‘Die’ = bare silicon; ‘package’ = enclosure + electrical connections to the outside world
- •OSAT: outsourced assembly and testing; ATMP: assembly, testing, marking, packaging
- •Manufacturability checks: design-rule checks (DRC) and foundry validation before fab
3nm vs 28nm: what ‘nm’ really means and why leading-edge is so hard
Sharan explains how “nanometer” has shifted from a literal transistor dimension to a node label correlated with density and efficiency. He illustrates the extreme complexity and cost of leading-edge manufacturing equipment, using ASML’s EUV machines and the logistics of shipping them as examples.
- •‘nm’ today is partly branding/labeling; still indicates relative density/advancement
- •Smaller nodes generally improve performance-per-watt and transistor density
- •ASML EUV tools are extraordinarily complex and cost ~$250–$300M per unit
- •Leading-edge manufacturing has massive technical and capital barriers, shaping geopolitics and supply chains
Why Mindgrove chose 28nm: the ‘Goldilocks’ node for embedded products
Mindgrove deliberately targets 28nm because its products serve embedded markets where cost, robustness, and specific electrical characteristics matter more than smartphone-class peak performance. Sharan ties node choice to user experience (lag, buffering, battery) and the economics of scaling a startup chip business.
- •28nm chosen for embedded needs: sufficient performance + optimized power at lower cost
- •3nm helps high-throughput mobile workloads but is exponentially more expensive
- •Embedded devices (controllers, appliances, soundboxes) often don’t need cutting-edge nodes
- •Node evolution driven largely by smartphone constraints: size, power, and integration pressure
SecureIoT: India’s commercial-grade microcontroller SoC built on Shakti
Sharan introduces Mindgrove’s first chip prototype, SecureIoT, describing it as a security-oriented IoT SoC targeting access control, biometrics, appliances, and industrial controllers. He highlights the use of IIT Madras’s Shakti C-Class processor and what “commercial-grade” means compared to a technology demo.
- •SecureIoT SoC targets biometric/access control, Aadhaar-like verification, appliances, industrial control
- •Security focus: hardware contribution within a broader security ecosystem
- •Built around Shakti C-Class processor from IIT Madras RISE Lab
- •‘Commercial-grade’ vs ‘technology demonstrator’: sellable reliability, licensing, validation, and product readiness
SoC architecture made simple: what’s inside a ‘system on chip’
The episode breaks down what qualifies as an SoC: processor plus memory hierarchy, peripherals, interconnect, and the components needed to function as a complete system. Sharan compares SecureIoT to smartphone SoCs like Snapdragon, emphasizing scale differences and integration tradeoffs.
- •SoC = processor + caches/registers + peripherals + interconnect fabric
- •Snapdragon is an SoC; SecureIoT is also an SoC but far smaller in die area
- •SoC size discussed qualitatively; packaged chip is about fingernail-sized
- •Integration choices depend on target application and required peripherals/features
Vision SoC: the next product line for computer-vision edge devices
Sharan previews Mindgrove’s next chip, Vision SoC, aimed at camera-centric and vision-processing workloads such as CCTV and infotainment. He explains it as a multi-core evolution (from single-core SecureIoT to a quad-core design in progress) and frames it as the start of a family of chips rather than a one-off.
- •Vision SoC targets edge vision: CCTV, infotainment, camera pipelines and processing
- •Designed as multi-core (at least four cores planned); design still customer-driven and not frozen
- •DLI approval supports this next chip program
- •Product strategy: build families/variants over time, not single chips
India Semiconductor Mission: strategic autonomy, import bill, and jobs
The conversation broadens to why nations are investing heavily in semiconductors (CHIPS Act, Japan, Germany, India). Sharan argues chips are “the new oil,” critical for sustaining a digital economy, reducing strategic dependency, and creating a large skilled-employment base via ecosystem effects beyond fabs themselves.
- •Digital public infrastructure (payments, services) increases chip dependence and import exposure
- •Semiconductors framed as strategic resource: resilience and sovereignty in supply chains
- •Fabs alone create thousands of jobs, but ecosystem spillovers multiply job creation (suppliers, maintenance, services, compliance)
- •Need to create millions of skilled, aspiration-matching jobs; entrepreneurship is positioned as essential
RISE Lab and the ‘industry–academia bridge’: moving from demo to product
Sharan explains RISE Lab as a multi-professor, multi-student collaborative environment that builds breadth and depth needed for chip design and systems validation. The discussion highlights how academia proves feasibility (technology demonstrators), while startups commercialize—symbolized by IIT Madras Research Park’s literal ‘industry-academia bridge.’
- •RISE Lab: collaborative research hub spanning chip design and system/software enablement
- •Demonstrators validate designs with real toolchains and benchmarks (compilers, open-source stacks)
- •Commercialization requires product engineering, licensing, validation, and customer fit
- •IITM incubation + Research Park infrastructure helps startups cross from lab proof to market reality
Working with government and institutions: ‘IITM speed vs startup speed vs government speed’
Sharan describes navigating institutional complexity by being systematic and compliance-focused, while acknowledging different operational tempos. He praises the DLI/ISM teams for being engaged and responsive despite unavoidable procedural layers, and notes the need for dedicated effort to manage statutory and reporting demands.
- •Three speeds: startup fastest, IITM middle, government slowest—but improving for semiconductors
- •Government support described as pragmatic: remove obstacles, set environment, then let startups execute
- •Handling bureaucracy through rigorous documentation and compliance ‘beyond the minimum’
- •Dedicated team/processes needed to interface with government requirements and accountability structures
How they moved fast: 8-month chip execution + the real costs (tools, licenses, infra)
Sharan recounts that SecureIoT’s design execution took ~8 months, enabled by prior market discovery and access to IITM infrastructure. He clarifies why universities can tape out demos but not sell chips due to licensing, and how incubator-negotiated commercial tool licenses and shared facilities are crucial to building sellable silicon.
- •~1 year spent figuring out what to build; ~8 months to execute the first chip design
- •IITM/Pravartak provide expensive infrastructure and testing capabilities that startups can access
- •University EDA licenses enable prototyping but not commercial sales; commercial licenses are far costlier
- •Tooling cost scales exponentially with chip sophistication, influencing node and product choices
‘It will come when you make it’: Shakti’s commercialization and the insanity of silicon
Sharan shares the turning point: asking when Shakti would be available as a chip and being told to build it themselves. He explains why making silicon is dominated by giant incumbents and why capital can be spent instantly on advanced nodes—making strategic restraint and clear business paths essential for startups.
- •Origin story: during the pandemic, Mindgrove shifted from systems to chip-first strategy using Shakti’s ‘middle ground’ fit
- •Professor’s push: IIT can prove tech, but commercialization needs someone to take ownership
- •Why silicon companies are huge: extreme capex, tooling/licensing, risk, and long cycles
- •Investor mindset: balance failure risk with upside; success can be massive, failure is common in startups
Failure tolerance, personal resilience, and finding balance outside the lab
The closing section emphasizes the ability to fail safely and learn when to persist versus stop. Sharan shares a formative failure story from ETH Zurich and connects it to handling startup setbacks, then ends with how he decompresses—sleep, cooking, cleaning, cricket, and ‘mindless’ movies.
- •Ecosystem value: enables ‘safe failure’—but founders must accept and process setbacks
- •Stubbornness is an asset and a liability; knowing when to stop matters
- •ETH Zurich story: failing a required math course once, passing on the second try, and the long-term resilience it built
- •Relaxation routines: sleep, cooking, stress-cleaning, cricket/ IPL highlights, and light entertainment
