Best Place To BuildSharan Srinivas | CTO, Mindgrove Technologies | “You have to be crazy to want to make silicon”| Ep.9
CHAPTERS
- 0:30 – 4:39
Series A raise + DLI approval: what the new capital enables
Sharan breaks down Mindgrove’s Series A round, why existing investors doubled down, and what the fresh capital will be used for. He also explains the Government of India’s Design Linked Incentive (DLI) scheme and how incentives are tied to milestones.
- •Series A update: returning investors doubling down + new investors joining
- •Total capital raised (~$8M) and what it’s earmarked for (more chips, selling what they build)
- •DLI approval: ~₹15 crore incentives tied to specific milestones
- •Why semiconductor startups require patient, long-horizon capital
- 4:39 – 7:11
Why semiconductors underpin “everything digital”
The conversation zooms out to explain why chips sit underneath almost every modern product and service—from cloud storage to QR-code payments. Sharan uses everyday examples to show how deeply embedded semiconductors are in daily life.
- •Semiconductors as the foundation of digital services and devices
- •Examples: cloud servers, smartphones, UPI soundbox, induction stoves
- •Passive components and electronics as part of the broader ecosystem
- •Why society’s push toward digitization increases chip dependence
- 7:11 – 9:34
Who does what: fabless design houses, integrated players, and pure-play foundries
Sharan maps the industry structure and where Mindgrove fits. He contrasts fabless companies with integrated device manufacturers and pure-play foundries, using well-known global examples.
- •Mindgrove as a fabless design-and-sell company (manufacturing outsourced)
- •Examples of fabless: Qualcomm, Nvidia; integrated: Intel, Samsung
- •Foundries like TSMC: manufacture only, don’t design end products
- •Where design ownership vs manufacturing scale shows up in business models
- 9:34 – 12:25
From wafer to packaged chip: manufacturing, dicing, OSAT/ATMP explained
A practical walkthrough of how chips are made and delivered—from 12-inch wafers to diced dies to packaged integrated circuits. Sharan clarifies packaging and the role of OSAT/ATMP providers in assembly and testing.
- •12-inch silicon wafer manufacturing and why layout must satisfy design rules
- •Design rule checks and manufacturability validation (dry runs, foundry checks)
- •Dicing wafers into dies; what a ‘die’ is vs what a ‘package’ is
- •OSAT vs ATMP: outsourced assembly/testing and assembly/testing/marking/packaging
- 12:25 – 18:15
3nm vs 28nm: what ‘nanometer’ really means (and why EUV is so expensive)
Sharan demystifies “nm” as a node label that no longer maps cleanly to a single transistor dimension, while still signaling density and capability. He also illustrates the complexity and cost of leading-edge manufacturing tools like ASML EUV systems.
- •‘nm’ as node branding/labeling more than a literal dimension today
- •Smaller nodes generally mean higher density and better performance per watt
- •Leading-edge tooling complexity (ASML) and extreme capital intensity
- •Why the manufacturing ecosystem is globally concentrated among a few giants
- 18:15 – 20:50
Why Mindgrove chose 28nm: performance-per-watt vs cost for embedded use cases
The discussion shifts from “smaller is better” to “fit-for-purpose,” explaining why embedded systems often don’t need cutting-edge nodes. Sharan ties node choice to cost, power, electrical characteristics, and real-world product requirements.
- •3nm offers superior performance-per-watt but is exponentially costlier
- •Embedded devices often don’t need smartphone-class compute density
- •28nm positioned as a “Goldilocks node” for Mindgrove’s target markets
- •Older nodes (90/65nm) can still be sufficient for many IoT-style products
- 20:50 – 23:21
SecureIoT SoC: Mindgrove’s first commercial-grade chip and target applications
Sharan introduces SecureIoT, Mindgrove’s first prototype-to-product effort, and explains where it’s used. He emphasizes hardware’s role in security and lists the embedded applications the chip is designed to serve.
- •SecureIoT: IoT-focused SoC with a hardware security component
- •Use cases: biometrics/access control, Aadhaar verification, appliances, industrial controllers
- •Importance of voltage/electrical characteristics in embedded designs
- •Positioning as a practical, deployable chip rather than a lab prototype
- 23:21 – 24:13
Commercial-grade vs technology demonstrator: what changes after tape-out
Sharan clarifies the gap between proving something works and building something that can be sold reliably. He frames this as the difference between R&D outcomes and production-ready engineering and productization.
- •Technology demonstrator: proof of capability; commercial-grade: sellable, supportable product
- •R&D vs production engineering requirements aren’t the same
- •Why prior Shakti tape-outs existed but weren’t commercial products
- •What Mindgrove adds to turn a research outcome into a market-ready offering
- 24:13 – 25:39
SoC fundamentals: what ‘system-on-chip’ includes beyond a CPU
The conversation gets architectural, defining what makes something an SoC. Sharan breaks down the major blocks—processor, memories, peripherals, and interconnect—and contrasts tiny embedded SoCs with smartphone-scale platforms like Snapdragon.
- •SoC = full system on a single die (not just a processor core)
- •Key blocks: CPU, caches/registers, peripheral controllers, interconnect fabric
- •Smartphone SoCs vs embedded SoCs: huge differences in die area and scope
- •SecureIoT as a much smaller SoC class compared to flagship mobile chips
- 25:39 – 27:55
Vision SoC roadmap: multi-core design driven by customer discovery
Sharan previews Mindgrove’s next chip family, Vision SoC, built for computer-vision workloads. He explains why the design remains flexible while they talk to customers, and how they think in terms of chip families and variants.
- •Vision SoC aimed at CCTV, infotainment, and embedded vision pipelines
- •Moving from single-core SecureIoT to a multi-core (quad-core+) architecture
- •Customer conversations influence feature freeze and final spec decisions
- •Long-term plan: families of chips with multiple variants, not one-offs
- 27:55 – 34:52
India Semiconductor Mission: sovereignty, import bills, and job creation logic
Sharan explains why countries are aggressively investing in semiconductors and what it means for India specifically. He ties chip independence to everyday digital infrastructure and frames fabs as seeds that grow large supporting ecosystems.
- •Semiconductors as ‘new oil’: strategic dependency risk and rising imports
- •Everyday digital life (payments, telecom, cloud) relies on many chip categories
- •Fabs create direct jobs, but far more indirect ecosystem jobs (suppliers, services)
- •Need for skilled job creation aligned with India’s demographic and education profile
- 34:52 – 41:42
RISE Lab + IIT Madras ‘industry-academia bridge’: how research becomes product
The episode turns to IIT Madras’ role: how RISE Lab’s breadth-and-depth model enables complex chip work, and how the Research Park and incubation structures help commercialization. Sharan uses the literal “industry-academia bridge” as a metaphor for tech transfer.
- •RISE Lab as an agglomeration of professors/students working across chip design + systems
- •Importance of software/toolchain/benchmarking to validate hardware innovation
- •The ‘bridge’ concept: IIT proves feasibility; startups take responsibility for commercialization
- •Incubation structure (IITM IC umbrella, Pravartak co-incubation; SNACS domain fit)
- 41:42 – 57:43
Startup execution reality: licenses, infrastructure, speed buckets, and an 8-month design cycle
Sharan discusses practical constraints that determine how fast a semiconductor startup can move: commercial EDA licenses, access to testing equipment, and institutional processes. He also compares ‘IITM speed,’ ‘startup speed,’ and ‘government speed,’ and explains how Mindgrove executed its first chip design in ~8 months after a year of figuring out what to build.
- •Speed buckets: startup fastest, IITM next, government slowest—but improving for semiconductors
- •Why commercial EDA licensing is a major cost/constraint vs university licenses
- •IITM/Pravartak infrastructure access as a force multiplier for execution
- •Timeline: ~1 year to decide what to build + ~8 months to execute first chip design
- 57:43 – 1:11:31
‘You have to be crazy to want to make silicon’: capital intensity, risk, and learning to handle failure
In the closing stretch, Sharan explains why most silicon companies are huge and how easy it is to burn enormous sums on advanced nodes and licenses. He then reflects on founder psychology—safe failure environments, knowing when to stop, and a personal story about nearly failing out of ETH Zurich that shaped his resilience—before ending with how he relaxes.
- •Why incumbents dominate: silicon is brutally capital-intensive and failure is expensive
- •Temptation to ‘spend $100M in five minutes’ via tools/licensing and advanced nodes
- •RISE/Shakti origin story: “It will come when you make it” as a push toward ownership
- •Failure mindset: grind vs knowing when to stop; ETH Zurich exam story as resilience training
