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The Twenty Minute VC

The $7B Startup Building AI Chips to Challenge Nvidia | Fractile Founder & CEO, Walter Goodwin

Walter Goodwin is the founder and CEO of Fractile, the British chipmaker taking on Nvidia in the race to make AI models answer faster. Fractile has raised $940M, including a $720M Series C that valued the company at $7.5BN.

Walter GoodwinguestHarry Stebbingshost

Nov 14, 20261h 15mWatch on YouTube

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CHAPTERS

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Chapter summaries

Fractile’s mission: selling chips while thinking like a frontier AI company
Walter Goodwin explains what Fractile builds—chips and rack-scale systems aimed at advancing frontier AI capabilities. He describes why the company needs expertise across ML research, manufacturing, thermals, and systems even though it monetizes by selling compute hardware.
- •Fractile builds chips and rack-scale systems focused on advancing frontier AI capability
- •The team spans ML researchers through to manufacturing/process experts and systems/mechanical specialists
- •The company monetizes by selling chips and racks rather than selling internal models
- •Walter says chip makers must understand how models and workloads evolve to place the right silicon bets
Vertical integration vs being “just” a chip company
Harry presses on whether the future is won by going full stack as major labs build their own chips. Walter argues a chip company can win without competing with customers, but only if it maintains deep, cross-stack understanding and internal ML research capability.
- •Harry questions whether vertical integration is required to avoid being squeezed
- •Walter distinguishes business model (sell chips) from necessary internal expertise (ML research and stack-wide vision)
- •Walter says Fractile does not intend to compete with customers by monetizing models
- •He emphasizes synthesizing signals across the ecosystem to avoid wrong product bets
What’s actually commoditizing in AI (and what isn’t)
Walter discusses “intelligence saturation” for some tasks and why economic pressure keeps pushing model efficiency forward. He argues frontier intelligence remains differentiated, and even open-model serving can avoid a race to the bottom when teams own more of the stack.
- •Some tasks show intelligence saturation, making certain model layers feel commoditized
- •Even “good enough” models face pressure to reduce the cost of intelligence
- •Walter says frontier intelligence is not commoditizing and still supports high margins for leaders
- •He cites DeepSeek’s efficient inference stack as an example of differentiation even when serving open models
Cloud compute as the layer most likely to commoditize—and why neo clouds look for chip differentiation
Walter claims competent neo clouds resemble one another, so cloud compute trends toward commoditization. He explains why neo clouds push into inference servers and why differentiated silicon could become a key advantage for them.
- •Walter says cloud compute is commoditizing: one competent neo cloud looks like another
- •Harry notes neo clouds try to vertically integrate into inference/model routing to defend their layer
- •Walter argues differentiated silicon can become a core differentiator for neo clouds
- •He frames adoption of new chip platforms as a bolder, higher-risk bet that can reshape economics
Specialized chips vs Nvidia: why “specialist” is no longer a niche
Walter praises Nvidia’s general-purpose strength, then explains why an evolving frontier creates room for more opinionated, workload-specific chips. He argues inference is now a huge market where specialization can be massive rather than niche.
- •Walter calls Nvidia extraordinary at high-quality products and volume systems
- •He says frontier evolution rewards companies built to “look around corners” and steer products accordingly
- •Fractile focuses on inference speed and memory bandwidth as an architectural priority
- •Walter argues a single workload (frontier inference) has become large enough to justify specialist chips
Why memory bandwidth bottlenecks LLM inference
Walter explains the two headline chip metrics—FLOPs and memory bandwidth—and how bandwidth scaling has lagged far behind compute scaling. He ties this directly to token generation speed, where repeatedly loading weights and context becomes the limiting factor.
- •FLOPs scaled dramatically over decades; memory bandwidth scaled far less, creating a widening gap
- •LLM inference generation is bottlenecked by loading model weights (and context) from memory
- •Walter links slow token generation on large models to insufficient bandwidth, not insufficient math units
- •He describes the physical constraint as limited wiring/interface capacity into the processor
SRAM vs DRAM trade-offs—and Fractile’s 3D-stacked memory approach
Harry asks whether SRAM or DRAM is better for inference latency; Walter explains the classic trade-off: SRAM is fast but small and expensive; DRAM is dense but constrained by interfaces. Walter describes Fractile’s attempt to reject the trade-off by stacking memory on top of logic to massively expand bandwidth.
- •SRAM is close and high-bandwidth but limited in capacity and costly per area
- •DRAM is dense/cheap but limited by the “beachfront” edge interface into the processor
- •Walter says Fractile is pursuing 3D stacking: placing memory on top of logic instead of beside it
- •He claims this enables many more vertical connections, increasing bandwidth dramatically
Long-running agents and context length: the inference workload chips don’t yet serve well
Walter argues reasoning models and long-running agents change inference requirements: more sequential generation, longer contexts, and huge capacity needs. He says fast inference chips can be constrained by memory capacity, creating a mismatch with emerging workloads.
- •Walter says test-time compute scaling and long-running agents drive massive sequential token generation
- •He claims today’s silicon hasn’t cracked the combination of very high speed plus high capacity
- •SRAM-based fast inference chips can be fast but run into capacity/context constraints
- •Walter frames the need as simultaneous high bandwidth, high speed, and high capacity for long contexts
From breakthrough to real production: what’s hard about scaling a chip startup
Harry challenges whether chip startups are truly in production or mostly marketing. Walter confirms Fractile has silicon back from foundries and discusses how real difficulty lies in scaling production amid constrained access to foundry capacity, HBM, and shared backend partners.
- •Walter says Fractile has produced silicon and is planning further tape-outs in the coming months
- •He highlights constraints: foundry capacity, memory capacity, and competition for the same resources
- •Walter claims many chips share similar process nodes/HBM and often the same backend partner
- •He positions manufacturing access and scaling volume as the central hurdle for new entrants
Why Fractile avoided an intermediary backend partner (and what that enables)
Walter explains how many major chip efforts reportedly rely on an intermediary backend partner, which can standardize platforms. He argues Fractile’s in-house backend and direct manufacturing relationships let it build more custom building blocks and potentially tap different supply-chain resources.
- •Walter describes the backend partner as handling last-mile physical design and foundry interaction
- •He says many efforts are rumored to use Broadcom as that intermediary
- •Walter argues platform standardization limits fundamental differentiation (same HBM, similar building blocks)
- •Fractile’s in-house approach enables custom work like memory stacking and alternative supply-chain choices
Tape-out isn’t the finish line: bring-up, yield, reliability, and ‘task zero’
Walter defines tape-out as sending the final chip layout file to the foundry to begin mask creation and fabrication. He argues the underestimated work is what comes after: silicon bring-up, system integration, manufacturability, yield, and getting a reference workload running across a full rack.
- •Tape-out is the handoff of the final layout file for mask creation and manufacturing
- •Errors after tape-out are extremely costly because fabrication is already underway
- •Post tape-out includes months of fab time, then lab bring-up from chip to tray to rack
- •Walter says Fractile tracks progress toward a reference workload running on a full rack (‘task zero’)
The bottleneck shifts to land and power—and why efficiency-focused chips matter more
Walter describes how constraints have moved from GPU shortage to broader supply chain limits and now increasingly to data center land and power. He argues this makes fit-for-purpose chips more important because power-limited data centers need higher throughput per megawatt at high speeds.
- •Walter says the limiting factor has shifted repeatedly over recent years
- •He describes today’s constraints as including land, power, grid connection queues, and ongoing memory/foundry shortages
- •He argues power limits make it vital to deploy chips that remain efficient even at high inference speed modes
- •He frames energy as a fundamental constraint and the reason better chips are economically urgent
China’s advantage on energy build-out—and a call for the UK/Europe to unlock power for AI
Harry asks whether the West is structurally disadvantaged vs China due to energy permitting and policy. Walter argues China has momentum via mega projects and suggests the UK/Europe could better leverage location-flexible data centers near renewables, while later emphasizing energy policy as key to growth.
- •Walter says China has ‘stolen the march’ via large power projects suited to colocated compute
- •He notes AI data centers can be placed where power is generated, even in remote locations
- •Walter argues renewables could play a big role if data centers are sited near generation (e.g., wind)
- •In the closing quickfire, he reiterates the UK must unlock more power (renewables and nuclear) to drive growth
Why inference demand expands: test-time compute as the capability ‘knob,’ plus economics and value capture
Walter explains his view that inference dominates long-run spend because training is a fixed cost and deployment is the point of building models. He discusses why costs must keep falling via algorithmic and hardware efficiency, where value might accrue (chips and frontier models), why complex multi-chip orchestration may be transient, and closes with Fractile’s funding and his outlook on timelines, Nvidia, and societal impact.
- •Walter argues inference is the main point economically: deployment must justify training’s fixed costs
- •He describes test-time compute (agent swarms and long runs) as the adjustable knob for higher capability
- •He says continuous innovation across algorithms and hardware is needed to meet compute/energy constraints
- •He suggests orchestration layers risk being least valuable if heterogeneity collapses over time as better unified chips emerge
- •Walter discusses Fractile’s $720M Series C and how capital enables roadmap depth, supply agreements, and broader systems work
- •In quickfire, he says model capability timelines are compressing for verifiable domains, predicts Nvidia could be a $10T business, and expresses excitement about real-world improvements from AI

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