Dwarkesh PodcastDylan Patel — The single biggest bottleneck to scaling AI compute
At a glance
WHAT IT’S REALLY ABOUT
AI compute scaling faces semiconductor tools, memory, and allocation bottlenecks
- Hyperscaler AI CapEx comes online over multiple years because large portions are pre-spent on long-lead items like turbines, power agreements, and data center buildouts well ahead of GPU deployment.
- In a supply-constrained world, older GPUs can become more valuable over time because model improvements raise the economic output per GPU faster than hardware obsolescence lowers it.
- By the late 2020s, the dominant bottleneck to scaling AI compute shifts upstream to semiconductor manufacturing—especially ASML’s EUV tool output—because fabs and tools have multi-year lead times that can’t be “sped up” like data centers.
- A major near-term constraint is memory (HBM/DRAM): AI demand pulls wafer capacity away from consumer devices, driving higher prices and potentially shrinking low- and mid-range smartphone/PC markets.
- Power, land, and permitting can be worked around via “behind-the-meter” generation and alternative sources, making them secondary constraints compared with chip, memory, and tool supply chains; space data centers are therefore unlikely this decade.
IDEAS WORTH REMEMBERING
5 ideasAI CapEx is front-loaded into long-lead infrastructure, not just GPUs.
Patel argues much of Big Tech’s headline CapEx is deposits and commitments for future power (turbines, PPAs) and data center construction years out, enabling rapid scaling later even if this year’s deployed GW is smaller.
Compute scarcity flips GPU “depreciation” intuition.
If demand is constrained by supply (not by newer chips), pricing reflects the value extractable today; with better models running cheaper per token, an H100 can be worth more now than years ago despite newer generations.
Early long-term compute contracts create enduring margin advantages.
Labs that locked multi-year deals earlier avoid today’s higher spot/shorter-term rates; late buyers may pay materially higher $/GPU-hour or accept revenue-share markups through hyperscaler platforms.
By ~2028–2030, ASML EUV tools become the hard scaling governor.
He estimates ~2 million EUV “passes” per 1 GW of leading-edge AI compute and ~3.5 EUV tools per GW; with EUV tool production only rising from ~70/year toward ~100+/year, tool availability constrains total chip output.
“Just use older fabs” is possible but inefficient and not equivalent.
Older nodes lose more than FLOP/price suggests because multi-chip scaling penalties (latency/bandwidth across dies/racks) dominate; architectural advances (networking, memory hierarchy, packaging) don’t port cleanly to 7nm-era designs.
WORDS WORTH SAVING
5 quotesan H100 is worth more today than it was three years ago.
— Dylan Patel
by '28, '29, the bottleneck falls to the lowest rung on the supply chain, which is ASML, right? ASML makes the world's most complicated machine, i.e. an EUV tool.
— Dylan Patel
it's funny to think about the numbers, right? Because we're talking about, oh, what's the gigawatt cost? It costs like fifty billion dollars roughly, right? Whereas what does three and a half EUV tools cost? That's like one point two, right?
— Dylan Patel
It is, it is much further out once you have energy constraints actually being a big bottleneck, once you have space, land permitting be a much bigger bottleneck as it subsumes more and more of the economy, um, and, and chips are no longer the bottleneck.
— Dylan Patel
it costs like close to fifty gigawatts. Now, obviously, we're not putting on fifty gigawatts this year
— Dwarkesh Patel
High quality AI-generated summary created from speaker-labeled transcript.
