Lex Fridman PodcastDavid Patterson: Computer Architecture and Data Storage | Lex Fridman Podcast #104
CHAPTERS
- 3:31 – 4:22
Microprocessors and the 50-year transformation of computing
David Patterson reflects on the biggest shift in computing over the last half-century: the microprocessor. He connects miniaturization, massive speedups, and ubiquity to Moore’s Law and the resulting societal inflection points.
- •Microprocessor enables room-sized computers to fit in phones
- •Orders-of-magnitude gains in speed and cost reduction
- •Ubiquity: more processors than people
- •Moore’s Law as the underlying driver and predictor of implications
- •Moments when computing visibly ‘leaked’ into everyday life (URLs, PC ads)
- 4:22 – 10:02
What’s inside a computer: the five classic components
Patterson breaks a computer into foundational parts and explains what a microprocessor is in that context. He uses intuitive analogies (brain vs brawn) to make processor internals accessible.
- •Five pieces: input, output, memory, arithmetic unit, control
- •Processor = control + arithmetic (ALU)
- •Microprocessor = processor on a single chip
- •Instruction execution as billions of simple operations per second
- •How simple ops compose into complex software behavior
- 10:02 – 13:27
Layers of abstraction and why they make complexity manageable
They discuss abstraction as the core coping mechanism for building complex hardware and software systems. Patterson outlines how learners can ‘peel the onion’ from high-level languages down to transistors, and why open source changes accessibility.
- •Abstraction layers as contracts/interfaces
- •10–20 layers in modern systems; onion-peeling mental model
- •Progression from Python to C to hardware understanding
- •Open source as visibility into implementations, not just usage
- •Growing movement toward open hardware visibility
- 13:27 – 15:20
Instruction sets as the hardware–software vocabulary (and why openness matters)
Patterson defines the instruction set as the vocabulary bridging software and hardware, then contrasts proprietary ISAs (x86, ARM) with emerging open alternatives. This sets up the motivation for RISC and later for RISC‑V.
- •Instructions: arithmetic, loads/stores, and control flow primitives
- •Instruction set architecture (ISA) as the core vocabulary/interface
- •x86 and ARM as dominant but proprietary ISAs
- •Licensing and control implications of proprietary ISAs
- •Open ISA as a catalyst for open implementations
- 15:20 – 29:59
RISC vs CISC: the controversy, the bet, and why simplicity won
They revisit the fierce 1980s debates over Reduced vs Complex Instruction Set Computing. Patterson explains why simple instructions plus good compilers can outperform complex instructions—and why compilers often failed to exploit CISC complexity.
- •CISC idea: powerful ‘polysyllabic’ instructions to ease programming
- •RISC idea: simpler instructions for faster, easier hardware design
- •Compiler reality: complex instructions are hard to generate and underused
- •Design-time and Moore’s Law favor simpler, evolvable microprocessors
- •Business inertia vs technical superiority as a key adoption barrier
- 29:59 – 36:02
Quantifying performance: benchmarks and the ‘three-factor’ execution-time model
Patterson explains how computer architecture shifted from intuition to measurement, including the role of benchmarks. He introduces the classic decomposition of runtime and shows how it clarified the RISC/CISC trade-offs.
- •‘Computer Architecture: A Quantitative Approach’ mindset shift
- •Benchmarks as shared, comparable workloads
- •Runtime factors: instruction count × CPI × clock cycle time
- •Why CPI (cycles per instruction) was decisive in RISC vs CISC
- •Parallelism and microarchitectural tricks show up as CPI reductions
- 36:02 – 39:36
What instructions really are: calculator keys, memory ops, and branches
They demystify instruction sets by mapping them to calculator operations and then highlighting what makes computers fundamentally more powerful: decision-making. Conditional branches are framed as the minimal primitive enabling complex control flow and behavior.
- •Core operations mirror calculator functions (add/subtract/multiply/divide)
- •Loads/stores correspond to calculator memory functions
- •Conditional branches enable decisions and general-purpose computation
- •Complex software emerges from simple primitives executed at scale
- •Instruction sets have remained surprisingly stable across decades
- 39:36 – 45:20
RISC‑V: an open ISA, open implementations, and modular extensibility
Patterson describes RISC‑V’s origin at Berkeley and why openness is its defining feature. He emphasizes the clean base ISA plus optional extensions model, and why that’s powerful for education, experimentation, and long-term ecosystem growth.
- •RISC‑V created (circa 2010) learning from earlier ISA mistakes
- •Open specification + open-source implementations (e.g., Verilog/VHDL)
- •Industry ‘thirst’ for an open ISA drove unexpected adoption momentum
- •Modular design: small core (~40 instructions) + optional extensions
- •Benefits: education, research flexibility, and avoiding ISA bloat
- 45:20 – 51:11
Where RISC‑V can win: cloud, mobile, and IoT market dynamics
They analyze the real-world friction of switching instruction sets, focusing on who controls the software stack. Patterson argues IoT/embedded is the most immediate opportunity, with cloud possible longer-term, and mobile the hardest due to app binaries.
- •Three markets: cloud (x86), mobile (ARM), IoT/embedded (fragmented)
- •Software distribution differs: app marketplaces vs controlled stacks
- •Binary compatibility locks in instruction sets for consumer ecosystems
- •IoT has less dominant ISA control and favors low-cost licensing
- •Cloud providers could shift if incentives and control align
- 51:11 – 58:37
Why ARM implementations vary: microarchitecture, licensing, and Apple’s edge
Lex asks why phones using the same ARM ISA can perform very differently. Patterson explains ARM’s licensing model (use ARM cores vs design your own) and how Apple’s custom microarchitecture and strong design teams produce superior results.
- •ISA sameness doesn’t imply identical performance
- •ARM business model: license cores or license the ISA to build custom cores
- •Custom microarchitecture is where ‘magic’ and differentiation happen
- •Apple built/acquired top CPU design talent and optimized implementations
- •Efficiency and performance are shaped by design choices beyond the ISA
- 58:37 – 1:08:16
Machine learning changes hardware: accelerators, matrix multiply, and a new golden age
Patterson links the slowdown of general-purpose CPU gains to the rise of domain-specific accelerators, especially for machine learning. He frames ML as both a demand shock (more compute) and a fortunate target (matrix multiply is highly accelerable).
- •Moore’s Law slowdown ends the old era of rapid general-purpose speedups
- •Future gains come from accelerators specialized to key workloads
- •ML dominance (data-driven methods) increases compute demand
- •Neural nets rely heavily on matrix multiply—ideal for acceleration
- •Hardware/software co-design returns as the central path forward
- 1:08:16 – 1:16:30
MLPerf and the role of benchmarks in cutting through hype
They discuss how standard benchmarks create fair comparisons and reduce marketing-driven claims. Patterson describes MLPerf’s rapid emergence, how it rewards complete hardware+software stacks, and how it shapes industry outcomes (including acquisitions and cancellations).
- •MLPerf created to standardize ML system performance evaluation
- •Benchmarks force credibility and expose weak software ecosystems
- •Hardware excellence without software support leads to market failure
- •Shared metrics improve engineering culture and buyer confidence
- •Social media + open source increase accountability for performance claims
- 1:16:30 – 1:28:22
Quantum computing realism, Moore’s Law debate, and what ‘slowing down’ means
Patterson argues quantum computing isn’t imminent for broad practical use and is likely data-center-bound for specialized tasks. He also clarifies the precise, measurable definition of Moore’s Law and critiques marketing-driven redefinitions while emphasizing ongoing (but slower) semiconductor progress.
- •Quantum computing: likely a decade-plus away from error-corrected utility
- •Not general-purpose; expected to live in specialized data-center settings
- •Moore’s Law defined as transistor doubling cadence—checkable with data
- •Distinguish ‘Moore’s Law stopped’ from ‘technology progress stopped’
- •Why messaging matters: complacency delays needed software/hardware innovation
- 1:28:22 – 1:36:53
RAID: from cheap disks to reliable, scalable storage—and what changed since
Patterson tells the origin story of RAID: using many inexpensive PC disks to beat large enterprise disks on cost and performance, then adding redundancy to solve reliability. He also describes the industry’s shift from spinning disks toward flash while noting reliability remains paramount in storage.
- •RAID = Redundant Arrays of Inexpensive Disks (performance + cost)
- •Reliability problem scales with many disks; redundancy makes it robust
- •With modest redundancy, arrays can be more reliable than single big drives
- •Major storage shift: HDDs to flash/semiconductor storage across devices
- •Reliability matters more for storage than compute due to irreversible loss
- 1:36:53 – 1:49:50
Teaching, wrestling, and the metrics of a life well lived
The conversation closes with Patterson’s philosophy of teaching as synergistic with research, lessons from wrestling on confidence and teamwork, and reflections on meaning and relationships. He emphasizes impact on people over transient metrics like money or paper counts.
- •Teaching forces clarity; student questions strengthen research thinking
- •Great researchers can also be great teachers (countering the stereotype)
- •Wrestling built physical and intellectual confidence and team-building skills
- •Life metrics: relationships, family, mentorship, and helping others
- •‘Nine magic words’ for marriage: ‘I was wrong. You were right. I love you.’
