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Former Intel CEO: Why This is the Best Time to Build Hardware

a16z's Raghu Raghuram and Guido Appenzeller sit down with Playground Global General Partner and former Intel CEO Pat Gelsinger to discuss the next wave of semiconductor innovation and the physical constraints shaping the AI buildout. Drawing on his experience designing Intel's 386 and 486 processors, Pat explains how AI could transform chip design, but also why faster design alone won't solve the industry's biggest problems. They examine the bottlenecks in manufacturing, memory bandwidth, advanced packaging, and power, and why today's explosion of specialized AI chips may eventually consolidate around a smaller number of architectures. They also discuss the potential for new memory technologies, the shift from copper to optical networking, and why energy capacity could become a major constraint on AI growth. Finally, they revisit Pat's VMware years to ask what virtualization might look like when infrastructure is built for agents rather than humans. Timestamps: 00:00 - Intro 01:00 - From tech school to Intel at 18 05:44 - The 486 and the birth of modern EDA 07:23 - How AI changes chip design 09:18 - Why silicon still takes nine months 14:49 - Will 100 AI chips converge to a few? 22:08 - Why HBM is a hideous memory 25:15 - How tall can chips get? 42:49 - Energy capacity equals economic capacity 48:42 - A VMware for agents Resources: Follow Pat Gelsinger on X: https://x.com/PGelsinger Follow Raghu Raghuram on X: https://x.com/RaghuRaghuram Follow Guido Appenzeller: https://x.com/appenz Stay Updated: If you enjoyed this episode, be sure to like, subscribe, and share with your friends! Find a16z on X: https://twitter.com/a16z Find a16z on LinkedIn: https://www.linkedin.com/company/a16z Listen to the a16z Show on Spotify: https://open.spotify.com/show/5bC65RDvs3oxnLyqqvkUYX Listen to the a16z Show on Apple Podcasts: https://podcasts.apple.com/us/podcast/a16z-podcast/id842818711 Follow our host: https://x.com/eriktorenberg Please note that the content here is for informational purposes only; should NOT be taken as legal, business, tax, or investment advice or be used to evaluate any investment or security; and is not directed at any investors or potential investors in any a16z fund. a16z and its affiliates may maintain investments in the companies discussed. For more details please see http://a16z.com/disclosures.

Pat GelsingerguestGuido AppenzellerhostRaghu Raghuramhost
Oct 9, 202653mWatch on YouTube ↗

At a glance

WHAT IT’S REALLY ABOUT

AI revives hardware, but power, memory, and manufacturing now bottleneck

  1. Pat Gelsinger describes a hardware “renaissance” where AI accelerates chip design, but fabrication, packaging, and rack-scale integration now dominate time-to-value.
  2. He argues that today’s explosion of AI inference accelerators will consolidate as workloads evolve, capital requirements bite, and major platforms pick a few hardware/software ecosystems to scale.
  3. He calls HBM the best available but fundamentally flawed, and predicts memory innovation—new materials and compute-memory co-design—will become unavoidable because AI is a memory-centric workload.
  4. He expects 3D stacking to advance but remain constrained by yield, thermals, and power delivery realities, making moderate stack heights the practical sweet spot.
  5. He claims energy capacity is becoming the binding constraint on AI expansion, pushing innovation in generation (including nuclear), high-voltage DC data centers, power electronics, cooling, and eventually optical interconnect plus more flow/circuit-like networking.

IDEAS WORTH REMEMBERING

5 ideas

AI is shrinking chip-design time; fabrication and packaging are now the real bottlenecks.

Gelsinger argues that AI makes the *design* step dramatically faster (months), but the system still can’t ship value until manufacturing, advanced packaging, and rack integration happen—often stretching to ~9 months or more. The practical frontier is reducing fab cycle time, mask costs, and packaging lead times so hardware can track rapidly changing AI workloads.

The “100 AI chips” moment is temporary; the market will converge to a few platforms.

He expects the current proliferation of AI accelerator startups to narrow because (1) over-specializing for transient workload phases (prefill/decode/mid-fill, etc.) becomes operationally unsustainable, (2) capital and scale requirements eliminate most entrants, and (3) major ecosystem players will select and software-enable a small number of “winners,” hiding heterogeneity behind abstraction layers.

AI turns memory into the central constraint—and may finally trigger real memory innovation.

Calling HBM “hideous” but necessary, Gelsinger highlights poor bit density, thermal issues (DRAM hates heat), bandwidth constraints (“shoreline bandwidth”), and power. He believes AI’s memory-centric nature and the new profitability of memory suppliers will finally fund new materials and architectures (e.g., ferroelectrics, non-capacitive, stackable high-density approaches).

3D packaging will grow, but manufacturing yield will cap stack height at modest levels.

He is skeptical that very tall stacks (e.g., 16–32 layers) will be practical because yield must improve superlinearly/exponentially as stack height increases; cracked dies can’t be rescued by redundancy. He predicts a “sweet spot” of modest logic/memory stacking (often 2–4 high for memory) plus added layers for power delivery, redistribution, and eventually integrated optics.

Optical is the future for I/O and networking—just not for the core compute-memory datapath.

Gelsinger supports optics broadly for I/O and cluster interconnect but dislikes heavy optical/electrical conversions inside the core compute-memory complex due to power losses: communication energy per bit is orders of magnitude worse than compute energy per operation. He predicts in-package optics and more optical switching (more circuit/flow-oriented) around 2028–2029, driven by predictable, large AI flows and the limits/cost of copper at scale.

WORDS WORTH SAVING

5 quotes

In a AI digital age, energy capacity equals economic capacity. Why build the new data center and buy the million GPUs if I can't power them? You're gonna see more and more defaults happening on many of those data center projects because the energy won't be there.

— Pat Gelsinger

W- whenever you have the technology to make something easy, that means the bottleneck moves somewhere else.

— Guido Appenzeller

Nothing's a chip anymore, it's a rack. It took me three months to design it, but it's nine months until I can actually start to use it.

— Pat Gelsinger

HBM is a hideous memory. It's just the best one that we got.

— Pat Gelsinger

I declared the death of copper about 25 years ago. Eventually I'll be right.

— Pat Gelsinger

Pat Gelsinger’s early Intel career and 486-era EDA originsAI-assisted chip design and where it breaks down (analog, SerDes)Manufacturing/packaging lead times and mask-cost constraintsProliferation and consolidation of AI accelerator startupsHBM limits and the return of memory R&D3D stacking, yield math, and thermal/power delivery integrationOptical I/O, scale-up fabrics, and optical circuit switching timelines (2028–2029)

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