a16zFormer Intel CEO: Why This is the Best Time to Build Hardware
CHAPTERS
- 0:00 – 1:02
Energy is the new limiter for AI: data centers, GPUs, and grid capacity
The conversation opens with a blunt constraint on the AI boom: power. Pat Gelsinger argues that in an AI-driven economy, national energy capacity becomes a hard cap on economic capacity—and that some data-center projects will fail simply because they can’t be powered.
- •“Energy capacity equals economic capacity” framing for the AI era
- •Risk of data-center project defaults due to insufficient power availability
- •AI infrastructure planning must treat electricity as a first-class resource, not an afterthought
- •Sets up the theme: once design gets easier, bottlenecks move to manufacturing, memory, networking, and power
- 1:02 – 3:36
From trade school to Intel at 18: learning by building real chips
Gelsinger recounts entering tech school as a teenager, joining Intel at 18, and rapidly moving from technician work to core CPU design. He describes a formative period where education and hands-on chip building reinforced each other daily.
- •Accidental scholarship to tech school and early exposure to computers
- •Intel recruitment at 18; early career acceleration from technician to design teams
- •Key roles across 286, 386, and leadership on 486 architecture/design management
- •Blending formal degrees (BS/MS/PhD path) with real production chip development
- 3:36 – 5:46
Industry-to-academia feedback loops: arguing with professors, advancing practice
He shares stories of challenging Stanford coursework with industry realities—sometimes proving academic designs didn’t work in practice. The discussion highlights why Silicon Valley’s proximity between universities and fast-moving companies creates unusually rapid iteration.
- •Example: disputing a carry-lookahead adder design based on 386 implementation experience
- •Built-in self-test debates: what’s elegant vs. manufacturable/practical
- •Role of Stanford figures (e.g., Ed McCluskey, John Hennessy) in shaping the era
- •Silicon Valley advantage: constant cross-pollination between research and product constraints
- 5:46 – 7:23
The 486 and the birth of modern EDA: inventing tools because none existed
Gelsinger explains that the 486 era helped establish what we now consider “modern” electronic design automation (EDA). With limited commercial tooling available, the team created foundational components—HDLs, compilers, early place-and-route, and timing automation.
- •486 as an early “modern EDA” chip program—before Verilog and mature tooling
- •Creation of Intel’s own HDL and compiler to enable RTL-style design flows
- •Early automated placement/routing/timing work with Berkeley (Sangiovanni-Vincentelli ecosystem)
- •How tooling breakthroughs became as important as the microprocessor itself
- 7:23 – 9:18
AI for chip design: what becomes easy—and what stays stubbornly hard
The panel explores whether today’s AI-driven chip design shift will be remembered like the EDA inflection point of the 486 era. Gelsinger argues AI can accelerate much of logic design and optimization, but analog domains (like SerDes) still resist automation without extensive silicon data.
- •AI-enabled design flows (e.g., “Jalapeno”) as a first-principles shift in methodology
- •Logic design increasingly AI-assisted; fewer experts can guide more exploration
- •Analog and mixed-signal blocks remain difficult to “AI” due to data and physics constraints
- •Prediction: future retrospectives may mark this as the start of a new chip-design era
- 9:18 – 13:39
The new bottleneck: nine-month silicon reality and the shift from chips to racks
Even if AI compresses design time, Gelsinger says production timelines dominate outcomes. He lays out why real-world deployment is governed by fab cycles, packaging complexity, and system-level integration—because the product is increasingly a rack-scale system, not a single chip.
- •Example timeline: ~3 months to design vs. ~9 months to usable silicon at scale
- •Fab cycle time limits; advanced packaging adds major schedule overhead
- •Mask costs and prototyping barriers slow iteration; need cheaper/ faster paths to silicon
- •“Nothing’s a chip anymore—it’s a rack”: integration and validation shift to system scale
- 13:39 – 22:08
Why there are 100 AI chips—and why most will disappear
The conversation turns to the explosion of AI accelerator startups and architectures. Gelsinger predicts consolidation, driven by workload evolution, capital intensity, and the reality that software-hardware co-evolution forces major platform “winner selection.”
- •Specialization (prefill/decode/midfill, reasoning models) risks over-fragmenting fleets
- •Workloads will shift; extreme specialization may not match future model evolution
- •Scale economics and capital requirements make 100 competing vendors unrealistic
- •Large buyers/platforms will pick winners based on hardware + software ecosystem fit
- 22:08 – 27:19
HBM is ‘hideous’—but memory innovation may finally be forced by AI economics
Gelsinger critiques HBM as a compromise with poor density and severe thermal/power constraints, yet still the best option today. He argues AI’s memory-centric nature and the newfound profitability of memory vendors may finally justify real breakthroughs after decades of stagnation.
- •HBM drawbacks: density limits, bandwidth “shoreline” constraints, heat/DRAM incompatibility
- •Historical reality: essentially no major new memory types in ~30 years beyond DRAM/SRAM/Flash
- •Memory R&D suppressed by brutal commoditization cycles; AI changes ROI expectations
- •Optimism for new materials (e.g., ferroelectrics) and new architectures; mentions funding a stealth memory company
- 27:19 – 32:14
How tall can chips get? The yield math and the practical stack sweet spot
They discuss 3D stacking limits and why very tall stacks become exponentially difficult to manufacture. Gelsinger expects modest stack heights to dominate, with additional layers needed for power delivery, redistribution layers, and future optical integration.
- •Stack value rises with height, but yield requirements rise exponentially—manufacturing becomes near-perfect or fails
- •Resilience helps (spares/bad block), but cracked die and hard failures still dominate outcomes
- •Likely sweet spot: ~2–4 high memory stacks; skepticism about 16–32 stacks in the near term
- •Realistic “thickness” already grows when adding power rails, RDL, and mixed-material integration
- 32:14 – 35:18
Compute-memory connectivity: skeptical on optical memory pools and PIM—bullish on optical I/O
Raghu and Pat contrast stacking with alternative approaches: optical links to distant memory and compute-in-memory (PIM). Gelsinger is skeptical of both due to conversion losses and workload constraints, but strongly supports optics for I/O as copper becomes untenable at scale.
- •Optical-to-electrical conversion (OEO) adds power loss; communication energy dwarfs compute energy
- •Large remote memory pools look attractive but can violate system-level energy economics
- •PIM has existed for decades; Gelsinger doubts it generalizes well across evolving workloads
- •Optics makes sense for I/O: “death of copper” (eventually); keep core compute-memory tight
- 35:18 – 42:39
Optics in the compute fabric by 2028–2029: scale-up vs scale-out and optical switching
Gelsinger forecasts a move to in-package optics (CPO/NPO) driven by the cost and feasibility limits of copper at scale. With AI traffic patterns being large and predictable, the panel discusses a shift toward optical/circuit-switched networks and a blurred boundary between scale-up and scale-out.
- •Copper waveguides get shorter and more expensive; optics can be cheaper at longer distances
- •Supply-chain maturity (lasers, packaging, thermals) is the main barrier—not physics
- •AI networking is predictable, high-volume flow-oriented—well-suited to circuit/optical switching (OCS)
- •Scale-up vs scale-out distinction may erode as fabrics converge in protocol and architecture
- 42:39 – 48:31
Power becomes the master constraint: nuclear, 800V DC data centers, and new physics
The discussion returns to the power stack—from national generation capacity to data-center distribution and chip-level efficiency. Gelsinger argues the U.S. underbuilt energy for years, and that meeting AI demand will require nuclear expansion, fewer conversion steps (e.g., 800V DC), and potentially radical new computing physics.
- •Claim: U.S. energy capacity flatlined ~10–15 years; AI makes that economically limiting
- •Nuclear as preferred baseload; renewables supply-chain dependencies and long turbine lead times
- •Data-center distribution shift: 800V DC and fewer conversion stages; new power electronics (e.g., vertical GaN, solid-state transformers)
- •CMOS energy efficiency stagnation cited; superconducting approaches proposed as step-change
- 48:31 – 53:14
A ‘VMware for agents’: virtualization and management for AI agent swarms
In closing, they explore how the next abstraction layer resembles virtualization—but targeted at AI agents rather than humans or OSes. Gelsinger describes the coming need for policy/guardrails, security, performance management, and “vMotion-like” mobility for agents across infrastructure.
- •Abstractions recur: algorithms, data structures, and virtualization-like layers keep returning
- •Agent swarms require management: security profiles, performance controls, governance dashboards
- •Conceptual mapping: “vMotion for agents,” migration, isolation, and lifecycle automation
- •Design constraint shifts: build platforms for agent usability and speed, while keeping humans in control via policies/constitutions
