This Indian Startup is Reinventing Chip Design | Neel Gala, CTO/Co-Founder, InCore Semiconductors
Neel Gala (guest), Amrut (host)
In this episode of Best Place To Build, featuring Neel Gala and Amrut, This Indian Startup is Reinventing Chip Design | Neel Gala, CTO/Co-Founder, InCore Semiconductors explores inCore uses RISC-V and generators to accelerate custom chip design The conversation demystifies what microprocessors, cores, subsystems, and SoCs are, and why chip development is slow, expensive, and uniquely risk-averse compared to software.
InCore uses RISC-V and generators to accelerate custom chip design
The conversation demystifies what microprocessors, cores, subsystems, and SoCs are, and why chip development is slow, expensive, and uniquely risk-averse compared to software.
Neel traces Shakti’s genesis at IIT Madras: limited access to modern proprietary ISAs pushed the team toward the emerging, simpler RISC-V ecosystem and an “if it doesn’t exist, build it” mindset.
InCore positions itself as an IP and subsystem/SoC solutions company, emphasizing that customers buy usable, integrated building blocks—not just a CPU core—and that IP delivery is largely “software” (RTL) with practical protection trade-offs.
The company’s SoC generator approach aims to cut the spec-to-RTL-freeze phase from months to weeks/days by enabling rapid PPA (power-performance-area) iteration and providing day-one collateral for software, emulation, and verification.
RISC-V is framed as a global “open opportunity” that breaks ISA monopolies and enables Indian strategic autonomy, while AI is described as a useful co-pilot but not yet trustworthy enough to replace humans in chip generation due to data scarcity and hallucinations.
Neel reflects on the founder transition (sell-before-build, customer discovery, first-customer risk), the long capital cycles of semicon, and the personal choices of staying in India to build foundational tech.
Key Takeaways
Chip design is slow because failure is catastrophically expensive.
A single bug can invalidate a multi-million-dollar prototype and restart a 12–18 month cycle, which drives heavy verification and a deeply risk-averse culture unlike “fail fast” software.
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ISAs are the choke point of hardware–software control.
Neel explains instruction sets as the shared “language” between hardware and software; keeping them proprietary enables ecosystem lock-in, licensing constraints, and monopoly-like market power.
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RISC-V matters because it’s permissionless, not just open.
RISC-V’s small base (dozens of instructions) and non-copyleft openness lowers barriers for new entrants to implement, customize, and commercialize without paying for ISA access or fearing restrictive clauses.
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A CPU core alone rarely sells; integrated subsystems win deals.
InCore’s thesis is that customers want a near-product SoC/subsystem—interconnect, peripherals, controllers, security, accelerators—so they can build chips quickly without stitching everything from scratch.
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SoC generators turn architecture exploration into rapid iteration.
By making SoC composition and trade-offs (PPA) configurable—down to “YAML-like” changes—teams can do many design iterations in days/weeks instead of weeks/months of manual RTL edits and reintegration.
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Parallelizing teams early is a major time unlock.
InCore aims to provide day-one collateral so software, emulation, and verification don’t wait on serialized milestones; this returns months of schedule to focus on the true differentiator (e. ...
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AI will help interfaces and verification sooner than full chip generation.
Neel argues that hallucinations, reproducibility demands, and lack of open training datasets make end-to-end generative chip design unreliable today; AI is better used as a co-pilot around deterministic generation tools.
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“Silicon-proof” credibility is the hardest commercial milestone.
The first customer is a high-stakes bet (recall risk), but once a design succeeds in real products, sales cycles compress dramatically because subsequent buyers trust proven silicon and references.
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Notable Quotes
“Imagine a chip which has a million transistors. You have to ensure that all million of them are working.”
— Neel Gala
“You spend $5 million getting the first prototype and it doesn't boot… Instead of 'Hello, world,' it says, 'Bye, bye, world.'”
— Neel Gala
“Innovation warrants curiosity, but curiosity warrants funding, warrants resources.”
— Neel Gala
“The transition… what academia teaches you to think is what's possible. What entrepreneurship demands you to think is what's needed.”
— Neel Gala
“RISC-V, beyond an open standard, is an open opportunity.”
— Neel Gala
Questions Answered in This Episode
InCore says it can reduce spec-to-RTL-freeze from ~4 months to days/weeks—what specific artifacts do you deliver on day one (software SDKs, testbenches, FPGA targets, reference boards), and what’s still custom work?
The conversation demystifies what microprocessors, cores, subsystems, and SoCs are, and why chip development is slow, expensive, and uniquely risk-averse compared to software.
Get the full analysis with uListen AI
Your SoC generator abstracts changes like editing a YAML file; what are the hard limits—what kinds of architectural changes still require manual RTL/verification effort?
Neel traces Shakti’s genesis at IIT Madras: limited access to modern proprietary ISAs pushed the team toward the emerging, simpler RISC-V ecosystem and an “if it doesn’t exist, build it” mindset.
Get the full analysis with uListen AI
How do you validate PPA claims early, before full physical design—what estimation models or flows do you use, and how accurate are they across nodes/foundries?
InCore positions itself as an IP and subsystem/SoC solutions company, emphasizing that customers buy usable, integrated building blocks—not just a CPU core—and that IP delivery is largely “software” (RTL) with practical protection trade-offs.
Get the full analysis with uListen AI
You keep Bluespec closed and ship Verilog to customers; what practical reverse-engineering risk remains, and how do customers debug issues without full visibility?
The company’s SoC generator approach aims to cut the spec-to-RTL-freeze phase from months to weeks/days by enabling rapid PPA (power-performance-area) iteration and providing day-one collateral for software, emulation, and verification.
Get the full analysis with uListen AI
RISC-V is open, but many SoCs need closed IP (DDR, PCIe, USB, Wi-Fi/Bluetooth); how do you integrate those constraints into a fast generator-driven workflow?
RISC-V is framed as a global “open opportunity” that breaks ISA monopolies and enables Indian strategic autonomy, while AI is described as a useful co-pilot but not yet trustworthy enough to replace humans in chip generation due to data scarcity and hallucinations.
Get the full analysis with uListen AI
Transcript Preview
So imagine a chip which has a million transistors. You have to ensure that all million of them are working. Now, imagine the odds against you, right? One transistor goes wrong, it's a bug, and you spend $5 million getting the first prototype and it doesn't boot. Instead of "Hello, world," it says, "Bye, bye, world." That's it. [chuckles] Yeah, you're dead in the waters.
To make chip designers better, faster, but not necessarily out of a job.
Oh, I, I don't think that's possible. I, I think we are here to... We're here to rule. Uh, he signed the docs, and he said, "If you truly believe in what you're saying, you shouldn't be applying to these universities." And right then and there, uh, you know, that's where I shred those documents. If the defense does not have a processor, if we are depending on foreign technologies from China, from Israel, from XYZ, to procure these chips, deploy it in our, you know, artilleries, imagine what the world would look like.
Hi, this is Amrut. We are at IIT Madras, my alma mater, and India's top university for people who like to build. We are here to meet some builders, ask them: What are you building? What does it take to build? And what makes IIT Madras the best place to build? [upbeat music] Hello, and welcome to the Best Place To Build Podcast. Today, I'm sitting with Neel Gala. He's the CTO of InCore Semiconductors, a fabless based out of IIT Madras. They are a Peak XV invested DLI awardee company. Hello, Neel.
Hi.
Neel, um, a lot of our conversation is going to revolve around microprocessors. So can you broadly explain what a microprocessor is, and then we'll start from there?
Sure. Um, I'll probably start with what I was told when, when I was in eighth, right? Uh, a processor is basically the brain of any electronic device, right? Uh, it's what controls that d- device, uh, how it communicates, how it interacts with the world in some sense, right? And in very layman terms, it would be, uh, sort of a, a universal translator, which can sort of convert human intent, which would typically be written in code, convert them to ones and zeros, and make your digital world dance, right? So at the end, every single device that you think is smart or you think is capable of working by itself has a processor in it, and it basically fundamentally figures out what needs to be done, how it needs to communicate to the world, and how it can serve human intentions at its best.
Hmm. Okay, so this, uh... Now, in the processor world, there are very few companies which actually build processors.
True.
They're all mega companies: NVIDIA, Intel, Arm. And in this pack of processor megawatts, um, India has developed this processor called the Shakti Processor, and you were there from day one-
Absolutely
... in the team that built Shakti.
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