CHAPTERS
From logic gates to multiply‑accumulate (MAC): why AI chips start here
The conversation begins at the lowest level of chip design—logic gates connected by physical wires—and builds toward the key arithmetic primitive for neural nets: multiply-accumulate. Reiner explains why MACs map directly onto matrix multiplication and why accumulation often uses higher precision than the multiply step.
Hand-building multiplication: partial products and AND gates
Reiner walks through long multiplication for two 4-bit values, showing how hardware generates partial products and then sums them. The key insight is that each partial product bit is just an AND of one bit from each operand.
Summing the grid efficiently: full adders, compressors, and Dadda multipliers
Most of the hardware cost is in summing the partial products rather than creating them. Reiner introduces the full adder as a 3-to-2 compressor and explains how repeatedly applying these compressors yields an area-efficient Dadda-style multiplier.
Bit-width scaling and FP4 vs FP8 “fungibility” in real chips
They connect the gate-level picture to GPU marketing metrics like FP4/FP8 throughput. Reiner explains why different precisions aren’t fully fungible in hardware, why scaling is roughly quadratic with bit-width, and why real ratios deviate due to floating-point exponent complexity and data movement constraints.
The hidden cost: muxes, register files, and why data movement dominates
Reiner models a traditional CPU/CUDA-core datapath: a register file feeding an ALU, with muxes selecting operands. Implementing “select register i” requires many gates (mask + OR reduction), and duplicating this for multiple operands makes movement far more expensive than the arithmetic itself.
Systolic arrays / tensor cores: baking loops into hardware to amortize movement
To fix the imbalance, tensor cores (systolic arrays) hardwire larger chunks of the matrix-multiply loop nest. By keeping weights local and streaming activations through, they increase compute per register-file access and reduce expensive cross-boundary wiring.
Loading weights efficiently: bandwidth vs time and the “trickle feed” approach
They address a practical question: if weights are local, how do they get there? The answer is to load them slowly through daisy-chained shifts, minimizing wiring bandwidth (die area) even if it takes multiple cycles, because weights are reused many times.
Sizing decisions that dominate chip design: array size vs register file size
Reiner frames many chip-architecture choices as “sizing” problems. Bigger systolic arrays improve amortization, while bigger register files improve flexibility and real workload performance; these compete for die area and power budgets.
Clock cycles, synchronization, and pipeline registers: what sets frequency
They move from spatial compute to timing: the clock synchronizes massive on-chip parallelism. Registers sample values on clock edges; clock frequency is limited by worst-case delay through combinational logic between registers (critical path), and designers insert pipeline registers to shorten that delay.
When pipelining breaks correctness: feedback loops and clock-limiting paths
Not all logic can be arbitrarily pipelined. Reiner explains that feedback (recurrence) paths—like an accumulator feeding itself—restrict where registers can be inserted without changing semantics, and these loops often determine the maximum safe clock rate.
FPGAs vs ASICs: LUTs, programmable mux fabrics, and the 10× overhead
Reiner explains the business and architectural trade-off: FPGAs are reprogrammable and deterministic but inefficient. Their flexibility comes from LUTs (truth tables) and pervasive muxing; implementing a simple gate can take tens of gates worth of LUT+mux machinery compared to a few gates in an ASIC.
Determinism and memory systems: cache vs scratchpad (and why CPUs vary)
They discuss why CPUs often have non-deterministic latency: caches introduce hit/miss variability depending on history and interference. Accelerators like TPUs often use scratchpads where software explicitly controls on-chip vs off-chip memory accesses, improving predictability.
Why CPU cores are “big,” and why a GPU looks like many tiny TPUs
Reiner contrasts CPU, GPU, and TPU organization. CPUs spend significant area on caches and control features like branch prediction; GPUs strip much of that control overhead and tile many smaller compute+memory units (SMs), while TPUs use fewer, larger coarse-grained matrix units plus vector units.
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