At a glance
WHAT IT’S REALLY ABOUT
From logic gates to TPUs: why AI chips favor systolic arrays
- The conversation builds an AI chip from first principles—logic gates to a multiply-accumulate (MAC)—to show why matrix multiplication maps naturally onto hardware.
- Bit-width drives compute cost roughly quadratically, which is a major reason low-precision (FP4/FP8) arithmetic is so advantageous for neural networks, though floating-point exponents reduce ideal scaling.
- Moving data (muxes/register-file reads) can cost far more area and energy than the arithmetic itself, motivating fixed-function blocks like systolic arrays that amortize data-movement overhead.
- Systolic arrays improve compute-per-communication by keeping weights local and streaming activations through, even if weights must be loaded slowly to minimize bandwidth (and die area).
- Clocking and pipeline registers set performance via critical paths and feedback loops, while architectural choices (FPGA vs ASIC, cache vs scratchpad, GPU vs TPU organization) trade flexibility, determinism, and data-movement efficiency.
IDEAS WORTH REMEMBERING
5 ideasMACs map directly onto matrix multiplication’s inner loop.
Matrix multiply is a nested loop where each output element repeatedly performs output += a*b; hardware therefore optimizes around fused multiply-accumulate at massive scale.
Arithmetic cost grows roughly with bit-width squared, so lower precision is disproportionately cheaper.
A p×q multiply produces p·q partial products and needs ~p·q full-adder compressions, making smaller formats dramatically smaller/faster; ideal scaling is tempered in floating point by exponent handling.
Selecting operands can be more expensive than computing on them.
A register-file read requires muxing among many sources; an n-to-1 mux over p-bit words costs ~n·p ANDs plus ~(n−1)·p ORs, and MACs may require multiple such reads per operation.
Systolic arrays win by amortizing register-file and routing overhead across many MACs.
Instead of repeatedly fetching arbitrary operands for each MAC, the design “bakes in” higher-level loop structure so a large grid of MACs reuses local data and reduces expensive global selection/wiring.
Keeping weights local is key; loading them slowly can be optimal.
Weights are reused across many input vectors, so they’re stored in local registers near compute; to avoid wide, area-expensive buses, weights can be daisy-chained in over many cycles (optimize bandwidth/area over load time).
WORDS WORTH SAVING
5 quotesSo this circuit I've described here, almost all of the cost, like, uh, seven-eighths of the cost, uh, is, is in the reading and writing the register file, and only a tiny fraction of the cost is in the logic unit itself. So this is the problem to solve.
— Reiner Pope
There is a global clock signal which drives all of these registers, and it says at a certain instance in time when the clock, uh, uh, strikes, um, uh, whatever value happens to be on this wire at that instant, that's what's gonna get stored in there.
— Reiner Pope
So, uh, taking that analogy, um, the, the, the, the thing that you need to be mindful of is if I've got two different paths through some logic... and the result from F and G have to sort of meet up at H, um, what can ... The, the thing that can go wrong is that F can get there early, and it meets, like, the previous value of G or the next value of G or something like that.
— Reiner Pope
The trade-off is that the first FPGA costs you ten thousand dollars, whereas the first ASIC you make costs you thirty million dollars because- uh, because of, uh, it, it requires an entire tape-out.
— Reiner Pope
So, uh, in a CPU you have the, the CPU... and then you have a cache system here... but whether or not you get a cache hit is dependent on the sort of ambient environment of the CPU. Like what other programs are running, what has run recently, what is the random number generator inside the cache system doing? And so, so that is a big source of non-determinism in, in the runtime of a CPU.
— Reiner Pope
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