Chip design from the bottom up – Reiner Pope

ℹ️ EPISODE INFO

Released

May 22, 2026

Duration

1h 20m

Channel

Dwarkesh Podcast

Watch on YouTube

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📝 EPISODE DESCRIPTION

New blackboard lecture with Reiner Pope: how do chips actually work - starting with basic logic gates, and working up to why GPUs, TPUs, FPGAs, and the human brain each look the way they do. Reiner is CEO of MatX, a new chip startup (full disclosure - I’m an angel investor). He was previously at Google, where he worked on software efficiency, compilers, and TPU architecture. 𝐄𝐏𝐈𝐒𝐎𝐃𝐄 𝐋𝐈𝐍𝐊𝐒

• Transcript: https://www.dwarkesh.com/p/reiner-pope-2 𝐒𝐏𝐎𝐍𝐒𝐎𝐑𝐒

• Crusoe was one of only five GPU clouds that made the gold tier in SemiAnalysis' most recent ClusterMAX report. Gold-tier providers like Crusoe delivered 5-15% lower TCO than silver-tier clouds, even with identical GPU pricing. This is because optimizations like early fault detection and rapid node replacement don't necessarily show up in the sticker price, but still matter a ton in the real world. Learn more at https://crusoe.ai/dwarkesh

• Cursor is where I do most of my work—from reading research papers to visualizing technical concepts to coding up internal tools for the podcast. Most recently, I used it to build two different review interfaces for my essay contest, one that anonymizes submissions for scoring and another that lets me see applicants' essays next to their resumes and websites. Whatever you're working on, you should try doing it in Cursor. Get started at https://cursor.com/dwarkesh

• Jane Street let me ask Ron Minsky and Dan Pontecorvo, two senior Jane Streeters, a bunch of questions about how they use AI. We discussed everything from the types of models they're training to how they think about the future of trading to why they're more bullish than ever on hiring technical talent. You can watch the full conversation and learn more about their open positions at https://janestreet.com/dwarkesh 𝐓𝐈𝐌𝐄𝐒𝐓𝐀𝐌𝐏𝐒 00:00:00 – Building a multiply-accumulate from logic gates 00:16:20 – Muxes and the cost of data movement 00:25:59 – How systolic arrays work 00:39:00 – Clock cycles and pipeline registers 00:51:40 – FPGAs vs ASICs 01:03:14 – Cache vs scratchpad 01:07:16 – Why CPU cores are much bigger than GPU cores 01:11:49 – Brains vs chips 01:15:22 – A GPU is just a bunch of tiny TPUs

🎤 SPEAKERS

• Dwarkesh Patel

  host

  Host of the Dwarkesh Patel podcast, interviewing researchers and technologists.

• Reiner Pope

  guest

  CEO of MatX, an AI chip company, speaking about chip architecture and design.

🧾 EPISODE SUMMARY

In this episode of Dwarkesh Podcast, featuring Dwarkesh Patel and Reiner Pope, Chip design from the bottom up – Reiner Pope explores from logic gates to TPUs: why AI chips favor systolic arrays The conversation builds an AI chip from first principles—logic gates to a multiply-accumulate (MAC)—to show why matrix multiplication maps naturally onto hardware.

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